1. Technical Field
The present invention relates to integrated circuits in general, and in particular to a method for manufacturing integrated circuit devices. Still more particularly, the present invention relates to a method for providing a fill pattern for an integrated circuit design.
2. Description of the Prior Art
Generally speaking, an integrated circuit device is a layered interconnected structure formed by a series of processing steps during which metallization, dielectrics, and other materials are applied to the surface of a semiconductor wafer. During some of the processing steps, a chemical-mechanical polishing (CMP) procedure is commonly employed to achieve the degree of planarity required for producing ultra-high density integrated circuit devices. The CMP procedure typically involves pressing a semiconductor wafer against a moving polishing surface that is wetted with a chemically reactive, abrasive slurry. The slurry can be basic, acidic or neutral, and generally contains alumina or silica particles. The polishing surface is typically a planar pad made of a relatively soft, porous material such as blown polyurethane.
During the CMP procedure, the semiconductor wafer is typically secured to a carrier via vacuum or a mounting medium such as an adhesive. A force load is applied to the semiconductor wafer through the carrier by a pressure plate so as to press the semiconductor wafer into frictional contact with the polishing pad mounted on a rotating turntable. Both the carrier and pressure plate rotate as a result of the driving friction from the rotating turntable directly attached to the pressure plate. The semiconductor wafer is then transported across the polishing surface for polishing.
When using the CMP procedure to remove unwanted portions of metal layer to leave thin lines of metals as interconnects, problems such as dishing may occur, which leads to a non-planar surface. The dishing effect is particularly serious when the polishing needs to be carried out until metal is left exclusively in previously etched lines without any metal on the surface of a dielectric layer. It has been found that a significant overpolish is typically needed, which results in erosion of the dielectric layer and dishing of metal below the surface of the dielectric layer. As a result, the thickness of the interconnects in overpolished areas is severely reduced, resulting in an increased sheet resistance when compared to interconnects in other areas of the semiconductor wafer. Additionally, an uneven topography is introduced on the surface of the semiconductor wafer after the CMP procedure, which will be repeated with slight attenuation after subsequent deposition of dielectric layers problems during subsequent steps of the fabrication process. In most cases, fill patterns are typically utilized to alleviate the above-mentioned problems.
Fill patterns are added to chips in order to maintain an even distribution of design levels across a chip, which reduces the potential for defects on the chip due to uneven CMP polishing during the chip manufacturing process. Having a certain percentage of coverage for metal, polysilicon and diffusion has been a universal requirement for foundries. In order to meet those coverage requirements (or chip density requirements), chip designers typically add xe2x80x9cdummyxe2x80x9d (electrically inactive) layout shapes on each required levels. It has been determined that the best manufacturing yields are achieved when the dummy layout graphics resemble the active layout graphics.
There are two commonly used methods for meeting chip density requirements:
(1) Add filler cells: For standard cell or gate array application specific integrated circuit (ASIC) designs, cells are generated that resemble library cells in form factor. Such cells are fully populated with transistors tied off to electrical power or ground, and are used to completely fill rows of the ASIC where no functional circuits or wiring has been placed. With such, the polysilicon and diffusion coverage requirements are typically met.
(2) Generate a fill pattern: For metal layers, a checkerboard pattern of metal squares is generated. The checkerboard pattern is placed in the xe2x80x9cwhite spacexe2x80x9d of the chip (areas of the chip where no design layers exist) to provide as much coverage as possible for the respective metal layers.
The problem with the first method is that it is limited to ASIC designs. It is made possible because of the regular structure of ASIC floor plans (rows of standard cell or gate array macros fitting a specific form factor). Filler cells are typically included in an ASIC library, and are placed as during post processing of an ASIC design. Full custom chip designs cannot use this methodology, as the design tools that implement such method must have xe2x80x9ca priorixe2x80x9d knowledge of the floor plan and power/ground bus structure. In addition, most design tools rely on design mapping generated by that tool during the place and route process. Unless the full custom design is placed and routed in the same manner as an ASIC, the first method will not work.
The second method is used for both ASIC and full custom chip designs, and is performed using vendor DRC tools. However, such tools are limited to generating the xe2x80x9ccheckerboardxe2x80x9d pattern and removing portions of that pattern from areas of the chip with active circuitry and wiring. The checkerboard pattern, while useful for obtaining desired chip density, does not resemble actual layout circuitry. The checkerboard pattern is a simple pattern that can be realized by the geometric manipulation commands of most vendor DRC tools.
The present disclosure provides an improved method for providing a fill pattern during the manufacturing of integrated circuit devices.
In accordance with a preferred embodiment of the present invention, a keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be placed. The map of areas from the keepout file is then overlaid with a fill pattern to yield a fill-pattern file. Fill patterns from the fill-pattern file is removed from locations that coincide with locations as defined by the keepout data to yield a final-fill file with crucial fill pattern data. The crucial fill pattern data from the final-fill file is overlaid on the design layout data in the chip design layout file to yield a complete design layout file. Finally, the design rule integrity and logical to physical correspondence of the complete design layout file is verified.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.